1. Field of the Invention
The present invention relates to an semiconductor integrated circuit, and more particularly, to an semiconductor integrated circuit with an operation testing function.
2. Description of Related Art
As is widely understood, in the manufacturing process of semiconductor memory device, firstly, many integrated memory circuits are formed on a semiconductor wafer, secondly, the operation of each integrated memory circuit are tested, moreover, the process of cutting the semiconductor wafer for memory chips, that is the dicing process is performed. Thereafter, only those memory chips deemed to be non-defective in the above operation test are packaged.
In a pre-dicing operation test, probes are pushed onto electrode pads on an integrated memory circuit. Input signals are supplied to the integrated memory circuit and output signals read from the integrated memory circuit via these probes. Therefore, this operation testing is called ‘probing’.
It is preferable that the frequency of the operation clock used in probing be the same as the frequency of the operation clock used when a semiconductor memory device is actually used. This is because when these frequencies do not match, a memory chip deemed to operate normally in probing may not operate normally in actual use.
However, the operation characteristics of semiconductor integrated circuits are improving each year and currently memory device with operation clock frequencies exceeding 150 MHz are appearing. In contrast, it is difficult to improve the operating speed of testing apparatus and equipment used in probing because of there structures. Therefore, the limit for the frequency of operation clocks that can be used in probing is 30 MHz.
Accordingly, in conventional probing technology, it has been impossible to adequately increase the yield of semiconductor memory device.